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Integrated Circuit Systems, Inc.
ICS950401
AMD - K8TM System Clock Chip
Recommended Application: AMD K8 Systems
Pin Configuration
*FS0/REF0 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS1* GND VDDREF REF2/FS2* SPREAD* VDDA GNDA CPUCLKT0 CPUCLKC0 GND VDDCPU CPUCLKT1 CPUCLKC1 VDD GND GNDA VDDA 48MHz GND VDD 24_48MHz/Sel24_48#* GND SDATA SCLK
Output Features: VDDREF 2 * 2 - Differential pair push-pull CPU clocks @ 3.3V X1 3 * 7 - PCI (Including 1 free running) @3.3V X2 4 * 3 - Selectable HT/PCI 66/33MHz @3.3V GND 5 * 1 - 48MHz, @3.3V fixed. *PCI33/HT66SEL# 6 * 1 - 24/48MHz @ 3.3V PCICLK33/HT66_0 7 * 3 - REF @3.3V, 14.318MHz. PCICLK33/HT66_1 8 Features: VDDPCI 9 * Up to 220MHz frequency support GND 10 * Support power management: PCI stop and stop PCICLK33/HT66_2 11 clocks controlled by I2C. NC 12 * Spread spectrum for EMI reduction PCICLK0 13 * Uses external 14.318MHz crystal PCICLK1 14 * I2C programmability features GND 15 VDDPCI 16 * Supports Hypes transport technology (HT66 output).
PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK_F *PCI_STOP# 17 18 19 20 21 22 23 24
48-SSOP/ TSSOP
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
Functionality
FS2 FS1 FS0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 PCI33_HT66 SEL# X 0 1 X X X X X X CPU Hi-Z X X 180.00 220.00 100.00 133.33 166.66 200.00 PCI33 Hi-Z X/6 X/6 30.00 36.56 33.33 33.33 33.33 33.33 PCI33_HT66 Hi-Z X/3 X/6 60.00 73.12 33.33/66.66 33.33/66.66 33.33/66.66 33.33/66.66 COMMENTS Tri-State Mode Bypass Mode Bypass Mode 10% under-clk 10% over-clk Athlon Compatible Athlon Compatible Reserved Hammer Operation
REF (2:0)
CPU DIVDER
Stop
CPUCLKC (1:0) CPUCLKT (1:0)
SDATA SCLK FS (2:0) PCI33/HT66SEL# PCI_STOP# SPREAD 24_48SEL#
Control Logic Config. Reg.
PCI DIVDER
Stop
PCICLK (5:0) PCICLK_F
X2
PCICLK33/HT66(2:0)
0499C--11/01/04
ICS950401
ICS950401
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PIN NAME *FS0/REF0 VDDREF X1 X2 GND *PCI33/HT66SEL# PCICLK33/HT66_0 PCICLK33/HT66_1 VDDPCI GND PCICLK33/HT66_2 NC PCICLK0 PCICLK1 GND VDDPCI PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK_F *PCI_STOP# SCLK SDATA GND 24_48MHz/Sel24_48#* VDD GND 48MHz VDDA GNDA GND VDD CPUCLKC1 CPUCLKT1 VDDCPU GND CPUCLKC0 CPUCLKT0 GNDA VDDA SPREAD* REF2/FS2* VDDREF GND REF1/FS1* PIN TYPE I/O PWR IN OUT PWR IN IN IN PWR PWR IN NC OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT I/O I/O IN I/O PWR I/O PWR PWR OUT PWR PWR PWR PWR OUT OUT PWR PWR OUT OUT PWR PWR IN I/O PWR PWR I/O DESCRIPTION Frequency select latch input pin / 14.318 MHz reference clock. Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Input for PCI33/HT66 select. 0= 66.66MHz, 1= 33.33MHz, PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input. PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input. No Connect PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin. Input select pin, Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Ground pin. 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. Power supply, nominal 3.3V Ground pin. 48MHz clock output. 3.3V power for the PLL core. Ground pin for the PLL core. Ground pin. Power supply, nominal 3.3V Complementory clock of differential CPU outputs. Push-pull requires external termination. True clock of differential CPU outputs. Push-pull requires external termination. Supply for CPU clocks, 3.3V nominal Ground pin. Complementory clock of differential CPU outputs. Push-pull requires external termination. True clock of differential CPU outputs. Push-pull requires external termination. Ground pin for the PLL core. 3.3V power for the PLL core. Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable spread spectrum functionality. 14.318 MHz reference clock / Frequency select latch input pin. Ref, XTAL power supply, nominal 3.3V Ground pin. 14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
0499C--11/01/04
2
ICS950401
General Description
The ICS950401 is a main clock synthesizer chip for AMD-K8. This provides all clocks required for Clawhammer and Sledgehammer systems. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS950401 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDDA = PLL2 VDDA = VDD for Core PLL VDDREF = REF, Xtal Pin 32 Pin 43 Pin 2
Skew Characteristics
Parameter Tsk_CPU_CPU Tsk_CPU_PCI Tsk_PCI_PCI Tsk_PCI33-HT66 Tsk_CPU_HT66 Tsk_CPU_HT66 Tsk_CPU_CPU Tsk_CPU_PCI Tsk_PCI_PCI Tsk_PCI33-HT66 Tsk_CPU_HT66 Tsk_CPU_HT66 time variant skew varies over V, T changes time independent skew not dependent on V, T changes Description Test Conditons
measured at x-ing of CPU, measured at x-ing of CPU, 1.5V of PCI clock measured between rising edge at 1.5V measured between rising edge at 1.5V measured between rising edge at 1.5V measured at x-ing of CPU, 1.5V of PCI clock measured at x-ing of CPU, measured at x-ing of CPU, 1.5V of PCI clock measured between rising edge at 1.5V measured between rising edge at 1.5V measured between rising edge at 1.5V measured at x-ing of CPU, 1.5V of PCI clock
Skew Window 250 2000 500 500 2000 500 200 200 200 200 200 200
Unit ps ps ps ps ps ps ps ps ps ps ps ps
0499C--11/01/04
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ICS950401
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
0499C--11/01/04
Not acknowledge stoP bit
4
ICS950401
Byte0: Functionality and Frequency Select
Bit
Pin #
PWD
7 6 5 4 3 2 1 0
0
0 0 0 0 0 0 0
45 48 1
Description Write disable (Write once)1 Spread Spectrum Enable. 0 = Disable; 1 = Enable 2 Reserved Reserved FS2 FS1 FS0 Write Enable 3
Notes: 1. Write Disable. A '1' written to this bit after a '1' is written to BYTE0/bit 0 will permanently disable writing to I2C until the part is powered off. Once the clock generator has been write disabled, the SMBus controller should still accept and acknowledge subsequent write cycles but it should not modify any of the registers. 2. Spread Pin SS Bit Spread Enable
0 0 1 1 0 1 0 1 Disabled Enabled Enabled Enabled
3. A '1' written to this bit after power-up will enable writing to I2C. Subsequent '0's written to this bit will disable modification of all registers except this single bit. When a '1' is written to Byte 0 Bit 7, all modification is permanently disabled until the device power cycles. Block write transactions to the interface will complete, however unless the interface has been previously unlocked, the writes will have no effect. The effect of writing to this bit does not take effect until the subsequent block write command. 4. Clarification on frequency select on power-up: i. Upon power-up, Byte0, bits (5:1) [FS(4:0)] are set to default hardware settings. ii. A '1' is written to Byte0, bit 0 to enable software control. iii. Every time Byte0 is written, frequency input defaults will be affected. iv. If a '0' is written to Byte0, bit0, the software control is disabled. Disabling software control does not cause the contents of Byte0 to default back to hardware setting for FS(4:0).
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ICS950401
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
7 8 22 21 18 17 14 13
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
PCICLK33/66_1 PCICLK33/66_0 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
37, 36 41, 40 45 48 1 28 31 11
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
CPUCLKT/C_1 (Note) CPUCLKT/C_0 REF2 REF1 REF0 24_48MHz 48MHz PCICLK33/66_2
Note: This bit can be optional to disable the CPUCLKT/ C1 clock pair; CPUCLKT=L, CPUCLKC=H.
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Read-Back Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
PIN#
22 21 18 17 14
PWD
0 0 0 0 0 0 0
DESCRIPTION
(Reserved) (Reserved) PCICLK5 (Note) PCICLK4 (Note) PCICLK3 (Note) PCICLK2 (Note) PCICLK1 (Note)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0 13 0 PCICLK0 (Note) Note: The above individual free running enable/disable controls are intended to allow individual clock outputs to be made free running. A clock output that has it's free running bit enabled will not be turned off with the assertion of either PCI_STOP#.
Bit 0 (Reserved) Note: Can be optionally used as PCI33_F enable control.
PIN# PWD 1 23 1 44 1 28 1 6 1 45 1 48 1 1 0 -
DESCRIPTION
PCICLK_F (Note) SPREAD 24_48SEL PCI33/66SEL# FS2 power-up latched pin state FS1 power-up latched pin state FS0 power-up latched pin state
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Byte Count Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
PIN# PWD
0 0 1 0 0 0 0 0
DESCRIPTION
VENDOR ID
REVISION ID
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 1
Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
DESCRIPTION (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note)
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 0499C--11/01/04
Note: Writing to this register will configure byte count and how many bytes will be read back. Default state is 07H = 7 bytes.
6
ICS950401
Byte 7: Reserved, Active/Inactive Register (1= enable, 0 = disable)
Byte 8: Single Pulse Mode Control Register (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Notes:
PIN# -
PWD 0 0 0 1 0 0 0 0
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 0 0 0
DESCRIPTION Single Pulse Trigger Single Pulse Activate ( R e s e r ve d ) ( R e s e r ve d ) ( R e s e r ve d ) ( R e s e r ve d ) ( R e s e r ve d ) ( R e s e r ve d )
ATPG Function: This feature is only used during processor Burn-In and is an optional feature for the clk vendor to implement. Two SMBus register bits are required to implement this feature: ATPG Mode Bit: Enables/Disables ATPG mode ATPG Pulse Bit: Triggers a single CPUclk pulse when set Assuming that the clock synthesizer is operating either in Normal mode or PLL bypass mode, following sequence may be followed to generate an ATPG pulse. 1. Set the Write Enable Bit (Byte/Bit 0) to program the Clock Synthesizer registers using the SM Bus. 2. Use the ATPG Mode Bit in the clock synthesizer configuration space to enable/disable the ATPG mode. When this bit is set, the ATPG mode is enabled and the differential CPU clock outputs are pulled in differential low state (CPUT = 0 and CPUC = 1). The ATPG mode also requires the USBclk (48MHz) to run as usual. All other clks (PCI, Ref, PCI33_66, SuperIO are not used by the ATPG mode therefore can either be left running or shut off. 3. Use the ATPG Pulse Bit in the clock synthesizer program space to generate the ATPG pulse. When the ATPG Pulse Bit is set, a differential ATPG pulse will be generated on the differential CPU clock pins. The pulse width of the ATPG pulse will be one CPU clock period. The CPU clock period in the ATPG mode is same as the one in Normal mode or PLL bypass mode. 4. Clear the ATPG Pulse Bit, as the clock synthesizer only recognizes 0 to 1 transition of the ATPG pulse bit for next ATPG pulse generation. 5. Use the ATPG Pulse Bit to generate the next ATPG pulse (set to 1). 6. If the ATPG Pulse bit is not set and the ATPG Mode Bit is cleared then the synthesizer should work in normal or PLL bypass mode.
0499C--11/01/04
7
ICS950401
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +3.8 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Input frequency Input Capacitance1 Clk Stabilization
1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 IDD3.3OP133 PD Fi CIN CINX TSTAB
CONDITIONS
MIN 2 VSS-0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz CL = 0 pF; Select @ 133MHz
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 180 600 mA A MHz pF pF ms
VDD = 3.3 V; Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq.
10 27
14.318
16 5 45 3
Guaranteed by design, not 100% tested in production.
0499C--11/01/04
8
ICS950401
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output Low Current Rise Edge Rate Fall Edge Rate VDIFF
1 1
SYMBOL ZO VOH2B VOL2B IOL2B
CONDITIONS VO = VX
MIN 15 1 18 2 2
TYP
MAX 55 1.2 0.4 7 7
VOL = 0.3 V Measured from 20-80% Measured from 80-20% Differential Voltage, Measured @ the Hammer test load (single-ended measurement) Change in VDIFF_DC magnitude, Measured @ the Hammer test load (singleended measurement) Common Mode Voltage, Measured @ the Hammer test load (single-ended measurement) Change in Common Mode Voltage, Measured @ the Hammer test load (singleended measurement) VT = 50% VT = VX
UNITS V V mA V/ns V/ns
0.4
2.3
V
VDIFF
-150
150
mV
VCM
1.05
1.45
V
VCM
-200
200
mV
dt2B 45 53 % Duty Cycle1 1 tjcyc-cyc2B 0 200 ps Jitter, Cycle-to-cycle Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpullup (external) = 1.5V, Min = Vpullup (external)/2-150mV; Max=(Vpullup (external)/2)+150mV
0499C--11/01/04
9
ICS950401
Electrical Characteristics - PCICLK, PCICLK33/HT66 (33MHz)
TA = 0 - 70 C; VDD = 3.3 V +/-5%; C L = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Edge Rate Fall Edge Rate Duty Cycle
1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1
CONDITIONS IOH = -12 mA IOL = 9.0 mA VOH = 2.0 V VOL = 0.8 V Measured from 20-60% Measured from 60-20%
MIN 2.4
TYP
10 1 1 45
MAX UNITS V 0.4 V -15 mA mA 4 4 55 250 V/ns V/ns % ps ps
dt1 tjcyc-cyc2B
VT = 50% Measured on rising edge @ 1.5V
Jitter, Cycle-to-cycle1 Jitter, Accumulated 1 Output Impedance
1
ZO
VO = VX
-1000 12
1000 55
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK33/HT66 (66MHz)
TA = 0 - 70 C; VDD = 3.3 V +/-5%; C L = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Edge Rate Fall Edge Rate Duty Cycle
1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1
CONDITIONS IOH = -12 mA IOL = 9.0 mA VOH = 2.0 V VOL = 0.8 V Measured from 20-60% Measured from 60-20%
MIN 2.4
TYP
10 1 1 45
MAX UNITS V 0.4 V -15 mA mA 4 4 55 250 V/ns V/ns % ps ps
dt1 tjcyc-cyc2B
VT = 50% Measured on rising edge @ 1.5V
Jitter, Cycle-to-cycle1 Jitter, Accumulated 1 Output Impedance
1
ZO
VO = VX
-1000 12
1000 55
Guaranteed by design, not 100% tested in production.
0499C--11/01/04
10
ICS950401
Electrical Characteristics - REF
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Edge Rate Fall Edge Rate Duty Cycle
1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V Measured from 20-80% Measured from 80-20%
MIN 2.4
TYP
16 0.5 0.5 45 0 -1000
MAX UNITS V 0.4 V -22 mA mA 2 2 55 1000 1000 V/ns V/ns % ps ps
dt5 tjcyc-cyc2B
VT = 50% Mesured on rising edge @ 1.5V
Jitter, Cycle-to-cycle1 Jitter, Accumulated 1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Edge Rate Fall Edge Rate Duty Cycle
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V Measured from 20-80% Measured from 80-20%
MIN 2.4
TYP
16 0.5 0.5 45 -1 0 0 20
MAX UNITS V 0.4 V -22 mA mA 2 2 55 1 500 200 60 V/ns V/ns % ns ps ps
dt5 tjabs5 tjcyc-cyc2B tjcyc-cyc2B ZO
VT = 50% VT = 1.5 V VT = VX, for 24_48MHz clock VT = VX, for 48MHz clock VO = VX
Jitter, Absolute
Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle1 Output Impedance
0499C--11/01/04
11
ICS950401
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248175 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
0499C--11/01/04
12
ICS950401
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950401yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0499C--11/01/04
13
ICS950401
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 48
10-0039
-Ce
b SEATING PLANE
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
(240 mil)
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil)
Ordering Information
ICS950401yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0499C--11/01/04
14

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